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1 idt and the idt logo are trademarks of integrated device technology, inc. industrial temperature range ? 2004 integrated device technology, inc. november 18, 2004 dsc-6238/5 t1/e1/oc3 wan pll with dual reference inputs IDT82V3012 functional block diagram osc reference input switch tie control block reference input monitor 0 osci tclr v dd v ss v ss c16o c8o c4o c2o c3o c1.5o f0o f8o f16o rsp tsp f0_sel0 f0_sel1 freerun normal holdover tdo tdi mon_out0 fref1 fref0 in_sel virtual reference flock invalid input signal detection f19o c6o jtag lock mode_sel0 mode_sel1 tie_en tms trst tck v dd v ss v dd v dd v ss rst f32o feedback signal state control circuit reference input monitor 1 mon_out1 c19pos c19neg frequency select circuit 0 frequency select circuit 1 f1_sel0 f1_sel1 c32o c19o dpll c2/c1.5 features ? supports at&t tr62411 and te lcordia gr-1244-core stratum 3, stratum 4 enhanced and stra tum 4 timing for ds1 interfaces ? supports itu-t g.813 option 1 clocks ? supports itu-t g.812 type iv clocks ? supports etsi ets 300 011, tbr 4, tbr 12 and tbr 13 timing for e1 interface ? selectable reference inputs: 8 khz, 1.544 mhz, 2.048 mhz or 19.44 mhz ? accepts two independent reference inputs which may have same or different nominal fr equencies applied to them ? provides c1.5o, c3o , c2o, c4o , c6o, c8o, c16o , c19o and c32o output clock signals ? provides 7 types of 8 khz framing pulses: f0o , f8o, f16o , f19o, f32o , rsp and tsp ? provides a c2/c1.5 output clo ck signal with the frequency controlled by the selected re ference input fref0 or fref1 ? holdover frequency accuracy of 0.025 ppm ? phase slope of 5 ns per 125 s ? attenuates wander from 2.1 hz ? fast lock mode ? provides time interval error (tie) correction ? mtie of 600 ns ? jtag boundary scan ? holdover status indication ? freerun status indication ? normal status indication ? lock status indication ? input reference quality indication ? 3.3 v operation with 5 v tolerant i/o ? package available: 56-pin ssop (green option available)
2 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range description the IDT82V3012 is a t1/e1/oc3 wan pll with dual reference inputs. it contains a digital phase-locked loop (dpll), which generates low jitter st-bus and 19. 44 mhz clock and framing signals that are phase locked to an 8 khz, 1.544 mhz, 2.048 mhz or 19.44 mhz input reference. the IDT82V3012 provides 9 types of clock signals (c1.5o, c3o , c6o, c2o, c4o , c8o, c16o , c19o, c32o ) and 7 types of framing signals ( f0o , f8o, f16o , f19o, f32o , rsp, tsp) for multitrunk t1/e1 and sts3/oc3 links. the IDT82V3012 is compliant with at&t tr62411, telcordia gr- 1244-core stratum 3, stratum 4 enhanced and stratum 4, etsi ets 300 011, itu-t g.813 option 1, and itu-t g.812 type iv clocks. it meets the jitter/wander tolerance, ji tter/wander transfer, intrinsic jitter/ wander, frequency accuracy, c apture range, phase change slope, holdover frequency accuracy and mtie (maximum time interval error) requirements for these specifications. the IDT82V3012 can be used in sy nchronization and timing control for t1, e1 and oc3 systems, or used as st-bus clock and frame pulse source. it also can be used in access switch, access routers, atm edge switches, wireless base station contro llers, or iads (integrated access devices), pbxs, line cards and sonet/sdh equipments. pin configuration figure - 1 IDT82V3012 ssop56 package pin assignment IDT82V3012 14 15 16 17 18 19 20 21 22 23 24 rst mon_out0 fref1 fref0 f19o osci f8o c1.5o lock c2o c4o flock f0_sel1 f0_sel0 c3o c8o c16o c32o f0o f16o 1 2 3 4 5 6 7 8 9 10 11 12 13 56 55 54 rsp tsp c6o v dd tdi tms trst tdo tck ic0 holdover freerun normal tie_en v dd v ss v ss c19o mode_sel0 mode_sel1 tclr in_sel 25 26 27 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 28 29 v dd v ss v dd v ss f32o v ss v dd c2/c1.5 ic2 f1_sel0 f1_sel1 c19neg c19pos mon_out1
3 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range table of contents 1 pin description............................................................................................................... ....................................................................................7 2 functional description ........................................................................................................ ..............................................................................9 2.1 state control circuit ....................................................................................................... ...........................................................................9 2.1.1 normal mode............................................................................................................... ...............................................................10 2.1.2 fast lock mode............................................................................................................ ..............................................................10 2.1.3 holdover mode ............................................................................................................. ..............................................................10 2.1.4 freerun mode.............................................................................................................. ...............................................................10 2.2 frequency select circuit .................................................................................................... .....................................................................10 2.3 reference input switch ...................................................................................................... .....................................................................10 2.4 reference input monitor ..................................................................................................... .....................................................................11 2.5 invalid input signal detection .............................................................................................. ....................................................................11 2.6 tie control block........................................................................................................... ..........................................................................11 2.7 dpll block.................................................................................................................. ............................................................................12 2.7.1 phase detector (phd)...................................................................................................... ..........................................................12 2.7.2 limiter................................................................................................................... ......................................................................12 2.7.3 loop filter ............................................................................................................... ...................................................................13 2.7.4 fraction block............................................................................................................ .................................................................13 2.7.5 digital control oscillator (dco).......................................................................................... ........................................................13 2.7.6 lock indicator ............................................................................................................ .................................................................13 2.7.7 output interface.......................................................................................................... ................................................................13 2.8 osc......................................................................................................................... ................................................................................14 2.8.1 clock oscillator .......................................................................................................... ................................................................14 2.9 jtag ........................................................................................................................ ...............................................................................14 2.10 reset, lock and tie application ............................................................................................ .................................................................14 3 measures of performance ....................................................................................................... ........................................................................16 3.1 intrinsic jitter ............................................................................................................ ...............................................................................16 3.2 jitter tolerance............................................................................................................ ............................................................................16 3.3 jitter transfer ............................................................................................................. .............................................................................16 3.4 frequency accuracy.......................................................................................................... ......................................................................16 3.5 holdover accuracy ........................................................................................................... .......................................................................16 3.6 capture range ............................................................................................................... .........................................................................16 3.7 lock range .................................................................................................................. ...........................................................................16 3.8 phase slope ................................................................................................................. ...........................................................................16 3.9 time interval error (tie)................................................................................................... .......................................................................16 3.10 maximum time interval error (mtie) ......................................................................................... .............................................................16 3.11 phase continuity ........................................................................................................... ..........................................................................17 3.12 phase lock time............................................................................................................ .........................................................................17 4 absolute maximum ratings ...................................................................................................... ......................................................................18 5 recommended dc operat ing conditions ........................................................................................... ..........................................................18 6 dc electrical characteristics ................................................................................................. .........................................................................18 6.1 single end input/output port................................................................................................ ...................................................................18 6.2 differential output port (lvds) ............................................................................................. ..................................................................19 7 ac electrical characteristics ................................................................................................ .........................................................................20 7.1 performance ................................................................................................................. ...........................................................................20 7.2 intrinsic jitter unfiltered ................................................................................................. ..........................................................................21 7.3 c1.5o (1.544 mhz) intrinsic jitter filtered ................................................................................. ..............................................................21 7.4 c2o (2.048 mhz) intrinsic jitter filtered ................................................................................... ...............................................................21 7.5 c19o (19.44 mhz) intrinsic jitter filtered .................................................................................. ..............................................................21 7.6 8 khz input to 8 khz output jitter transfer ................................................................................. ............................................................22 7.7 1.544 mhz input to 1.544 mhz output jitter transfer......................................................................... ....................................................22 7.8 2.048 mhz input to 2.048 mhz output jitter transfer......................................................................... ....................................................22 7.9 19.44 mhz input to 19.44 mhz output jitter transfer......................................................................... ....................................................23
4 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range 7.10 8 khz input jitter tolerance............................................................................................... ......................................................................23 7.11 1.544 mhz input jitter tolerance ........................................................................................... .................................................................23 7.12 2.048 mhz input jitter tolerance ........................................................................................... .................................................................24 7.13 19.44 mhz input jitter tolerance ........................................................................................... .................................................................24 8 timing characteristics ........................................................................................................ ............................................................................26 8.1 timing parameter measurement voltage levels ................................................................................. ...................................................26 8.2 input/output timing ......................................................................................................... ........................................................................26 9 ordering information .......................................................................................................... .............................................................................31
5 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range list of figures figure - 1 IDT82V3012 ssop56 package pin assignment ............................................................................. ................................................... 2 figure - 2 state control circuit ................................................................................................ ............................................................................ 9 figure - 3 state control diagram................................................................................................ ......................................................................... 9 figure - 4 tie control block diagram............................................................................................ .................................................................... 11 figure - 5 reference switch with tie control block enabled...................................................................... ...................................................... 12 figure - 6 reference switch with tie control block disabled..................................................................... ...................................................... 12 figure - 7 dpll block diagram ................................................................................................... ...................................................................... 13 figure - 8 clock oscillator circuit ............................................................................................. ......................................................................... 14 figure - 9 power-up reset circuit............................................................................................... ...................................................................... 15 figure - 10 timing parameter measurement voltage levels ......................................................................... ..................................................... 26 figure - 11 input to output timing (normal mode)................................................................................ .............................................................. 28 figure - 12 output timing 1..................................................................................................... ............................................................................ 29 figure - 13 output timing 2..................................................................................................... ............................................................................ 30 figure - 14 input control setup and hold timing ................................................................................. ............................................................... 30
6 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range list of tables table - 1 operating modes selection ............................................................................................. .....................................................................9 table - 2 fref0 frequency selection ............................................................................................. ....................................................................10 table - 3 fref1 frequency selection ............................................................................................. ....................................................................10 table - 4 input reference selection ............................................................................................. .....................................................................11 table - 5 c2/c1.5 output frequency control...................................................................................... ..............................................................14
7 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range 1 pin description name type pin number description v ss power 12, 18, 27 38, 47 ground. 0 v. all v ss pins should be connected to the ground. v dd power 13, 19, 26 37, 48 positive supply voltage. all v dd pins should be connected to +3.3 v (nominal). osci (cmos) i 50 oscillator master clock input. this pin is connected to a clock source. fref0 fref1 i 5 6 reference input 0 and reference input 1. these are two input reference sources (falling edge of 8 khz, 1.544 mhz and 2.048 mhz or rising edge of 19.44 mhz) used for synchronization. the in_sel pin determines which one of the two reference inputs to be used. see table - 4 for details. the frequency of the reference inputs can be 8 khz, 1. 544 mhz, 2.048 mhz or 19.44 mhz. these two pins are internally pulled up to v dd . in_sel i11 input reference selection. a logic low at this pin selects reference input 0 (fref0) and a logic high at this pin selects reference input 1 (fref1). the logic level on this input is gated in by the rising edges of f8o. this pin is internally pulled down to v ss . f0_sel0 f0_sel1 i 9 10 frequency selection inputs for fref0. these two inputs select one of the four possible frequencies (8 khz, 1.544 mhz, 2.048 mhz or 19.44 mhz) for the reference input 0 (fref0). see table - 2 for details. f1_sel0 f1_sel1 i 35 34 frequency selection inputs for fref1. these two inputs select one of the four possible frequencies (8 khz, 1.544 mhz, 2.048 mhz or 19.44 mhz) for the reference input 1 (fref1). these two pins are internally pulled down to v ss . see table - 3 for details. mode_sel0 mode_sel1 i 1 2 mode selection inputs. these two inputs determine the operating mode of the IDT82V3012 (normal, holdover or freerun). see table - 1 for details. the logic levels on these two pins are gated in by the rising edges of f8o. these two pins are internally pulled down to v ss . rst i4 reset input. pulling this pin to logic low for at least 300 ns will reset the IDT82V3012. while the rst pin is low, all framing and clock outputs are at logic high. to ensure proper operation, the device must be reset after it is powered up. tclr i3 tie control block reset. pulling this pin to logic low for at least 300 ns will reset the tie (maximum time interval error) control block and result in a realignment of the output phase with the input phase. this pin is internally pulled up to v dd . tie_en i56 tie control block enable. a logic high at this pin enables the tie control block while a logic low disables it. the logic level on this input is gated in by the rising edges of f8o. this pin is internally pulled down to v ss . flock i45 fast lock mode enable. when this pin is set to logic high, the dpll will quickly lock to the input reference within 500 ms. lock (cmos) o 44 lock indicator. this output pin will go high when the dpll is frequency locked to the input reference. holdover (cmos) o 52 holdover indicator. this output pin will go high whenever the dpll enters holdover mode. normal (cmos) o 46 normal indicator. this output pin will go high whenever the dpll enters normal mode. freerun (cmos) o 51 freerun indicator. this output pin will go high whenever the dpll enters freerun mode. mon_out0 o 7 frequency out-of-range indicator for fref0. a logic high at this pin indicates that fref0 is off the nominal frequency by more than 12 ppm. mon_out1 o 8 frequency out-of-range indicator for fref1. a logic high at this pin indicates that fref1 is off the nominal frequency by more than 12 ppm. c19pos c19neg (lvds) o 21 22 19.44 mhz clock output (lvds level). this pair of outputs is used for oc3/sts3 applications. c19o (cmos) o 43 19.44 mhz clock output (cmos level). this output is used for oc3/sts3 applications.
8 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range c32o (cmos) o 25 32.768 mhz clock output. this output is a 32.768 mhz clock used for st-bus operation. c16o (cmos) o 24 16.384 mhz clock output. this output is a 16.384 mhz clock used for st-bus operation. c8o (cmos) o 23 8.192 mhz clock output. this output is an 8.192 mhz clock used for st-bus operation. c4o (cmos) o 20 4.096 mhz clock output. this output is a 4.096 mhz clock used for st-bus operation. c2o (cmos) o 17 2.048 mhz clock output. this output is a 2.048 mhz clock used for st-bus operation. c3o (cmos) o 16 3.088 mhz clock output. this output is used for t1 applications. c1.5o (cmos) o 15 1.544 mhz clock output. this output is used for t1 applications. c6o (cmos) o 14 6.312 mhz clock output. this output is used for ds2 applications. c2/c1.5 (cmos) o 54 2.048 mhz or 1.544 mhz clock output. this output is a 2.048 mhz or 1.544 mhz clock signal. if the selected reference input (fref0 or fref1) is 8 khz, 2.048 mhz, or 19.44 mhz, the c2/c1.5 pin will output a 2.048 mhz clock signal. if the frequency of the selected reference input (fref0 or fref1) is 1.544 mhz, the c2/c1.5 pin will output a 1.544 mhz clock signal. refer to table - 5 for details. f19o (cmos) o 49 8 khz frame signal with 19.44 mhz pulse width. this output is used for oc3/sts3 applications. f32o (cmos) o 40 frame pulse st-bus 8.192 mb/s. this is an 8 khz 30 ns active low framing pulse, which marks the beginning of an st-bus frame. this framing signal is typically used for st-bus operation at 8.192 mb/s. f16o (cmos) o 39 frame pulse st-bus 8.192 mb/s. this is an 8 khz 61 ns active low framing pulse, which marks the beginning of an st-bus frame. this framing signal is typically used for st-bus operation at 8.192 mb/s. f8o (cmos) o 36 frame pulse. this is an 8 khz 122 ns active high framing pulse, which marks the beginning of a frame. f0o (cmos) o 33 frame pulse st-bus 2.048 mb/s. this is an 8 khz 244 ns active low framing pulse, which marks the beginning of an st-bus frame. this framing signal is typically used for st-bus operation at 2.048 mb/s and 4.096 mb/s. rsp (cmos) o 41 receive sync pulse. this is an 8 khz 488 ns active high framing pulse, which marks the beginning of a st-bus frame. this framing signal is typically used to connect to the siemens munich-32 device. tsp (cmos) o 42 transmit sync pulse. this is an 8 khz 488 ns active high framing pulse, which marks the beginning of an st-bus frame. this framing is typically used to connect to the siemens munich-32 device. tdo (cmos) o 29 test serial data out. jtag serial data is output on this pin on the falling edge of tck. this pin is held in high impedance state when jtag scan is not enabled. tdi i32 test serial data in. jtag serial test instructions and data are shifted in on this pin. this pin is internally pulled up to v dd . trst i30 test reset. asynchronously initializes the jtag tap controller by putting it in the test-logic-reset state. this pin is internally pulled up to v dd . it is connected to the ground for normal applications. tck i28 test clock. provides the clock for the jtag test logic. tms i31 test mode select. jtag signal that controls the state transitions of the tap controller. this pin is internally pulled up to v dd . ic0, ic2 -53, 55 these pins should be connected to v ss . name type pin number description
9 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range 2 functional description the IDT82V3012 is a t1/e1/oc3 wan pll with dual reference inputs, providing timing (clock) and synchronization (framing) signals to interface circuits for multitrunk t1/e1 and sts3/oc3 links. the details are described in the following sections. 2.1 state control circuit the state control circuit is an important part in the IDT82V3012. it is used to control the tie block and the dpll block as shown in figure - 2. the control is based on the result of invalid input signal detection and the logic levels on the mode_sel 0, mode_sel1, in_sel and tie_en pins. the IDT82V3012 can be operated in th ree different modes: normal, holdover and freerun. the operating mode is selected by the mode_sel1 and mode_sel0 pins, as shown in table - 1. figure - 3 shows the state control diagram. all state changes occur synchronously on the rising edge of f8o. three operating modes, normal (s1), holdover (s3) and fr eerun (s0) can be switched from one to another by changing the logic levels on the mode_sel0 and mode_sel1 pins. figure - 2 state control circuit figure - 3 state control diagram table - 1 operating modes selection mode selection pins operating mode mode_sel1 mode_sel0 00 normal 0 1 holdover 1 0 freerun 11 reserved state control circuit mode_sel1 mode_sel0 tie_en output of the invalid input signal detection f8o tie block enable/disable dpll block mode control in_sel s1 normal mode_sel1 = 0 mode_sel0 = 0 s3 holdover mode_sel1 = 0 mode_sel0 = 1 s0 freerun mode_sel1 = 1 mode_sel0 = 0 (invalid input reference signal) (valid input reference signal) a u t o t i e d i s a b l e a u t o t i e d i s a b l e tie enable (tie_en = h) a u t o t i e d i s a b l e a u t o t i e d i s a b l e a u t o t i e d i s a b l e t i e d i s a b l e ( t i e _ e n = l ) a u t o t i e d i s a b l e t i e e n a b l e (t i e _ e n = h ) reset * s4 short time holdover mode_sel1 = 0 mode_sel0 = 0 i n _ s e l t r a n s i e n t a u t o t i e d i s a b l e n o i n _ s e l t r a n s i e n t t i e e n a b l e (t i e _ e n = h ) n o in _ s e l t r a n s i e n t t i e d i s a b l e ( t i e _ e n = l ) i n _ s e l t r a n s i e n t a u t o t ie d i s a b l e s2 auto - holdover mode_sel1 = 0 mode_sel0 = 0 * note: after reset, the mode_sel1 and mode_sel0 should be initially set to '10' or '00'. auto tie disable (valid input reference signal) tie disable (tie_en = l)
10 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range the mode changes between normal (s1) and auto-holdover (s2) are triggered by the invalid input reference detection circuit and are irrelative to the logic levels on the mode_sel0 and mode_sel1 pins. at the stage of s1, if the input reference is invalid (out of the capture range), the operating mode will be changed to auto-holdover (s2) automatically. at the stage of s2, if no in_sel transient occurs and the input reference becomes valid, the operating mode will be changed back to normal (s1) automatically. if an in _sel transient is detected at the stage of s2, the operating mode will be changed to short time holdover (s4) with the tie control block automatically disabled. refer to ?2.5 invalid input signal detection? for more information. the mode changes between normal (s1) and short time holdover (s4) are triggered by the in_sel trans ient. at the stage of s1, if a voltage transient occurs on the in_sel pin, the operating mode will be changed to short time holdover (s4) automatically. at the stage of s4, if no voltage transient occurs on the in_sel pin, the operating mode will be changed back to s1 automatically. see ?2.3 reference input switch? for details. when the operating mode is changed from one to another, the tie control block is automatica lly disabled as shown in figure - 3 , except the changes from short time holdover (s4), holdover (s3) or auto- holdover (s2) to normal (s1). in the case of changing from s4, s3 or s2 to s1, the tie control block is enabled or disabled by the tie_en pin. 2.1.1 normal mode the normal mode is typically used when a slave clock source synchronized to the network is required. i n this mode, the IDT82V3012 provides timing (c1.5o, c3o , c2o, c4o , c8o, c16o , c19o, c32o ) and synchronization ( f0o , f8o, f16o , f19o, f32o , tsp, rsp) signals. all t hese signals are synchronous to one of the two input references. the nominal frequency of the input reference can be 8 khz, 1.544 mhz, 2.048 mhz or 19.44 mhz. after reset, the IDT82V3012 will take 30 seconds at most to make the output signals synchronous (phase locked) to the input reference. whenever the IDT82V3012 works in the normal mode, the normal pin will be set to logic high. 2.1.2 fast lock mode the fast lock mode is a submode of the normal mode. it allows the dpll to lock to a reference more quickly than the normal mode allows. typically, the locking time in the fast lock mode is less than 500 ms. when the flock pin is set to high, the fast lock mode will be enabled. 2.1.3 holdover mode the holdover mode is typically used for short duration (e.g., 2 seconds) while network synchroni zation is temporarily disrupted. in the holdover mode, the IDT82V3012 provides timing and synchronization signals that are not locked to an external reference signal, but are based on storage techni ques. in the normal mode, when the output frequency is locked to the input reference signal, a numerical value corresponding to the output fr equency is stored alternately in two memory locations every 30 ms. when the device is changed to the holdover mode, the stored value fr om between 30 ms and 60 ms is used to set the output frequency of the device. the frequency accuracy in the ho ldover mode is 0.025 ppm, which corresponds to a worst case of 18 fr ame (125 s per frame) slips in 24 hours. this meets the at&t tr62411 and telcordia gr-1244-core stratum 3 requirement of 0.37 ppm (255 frame slips per 24 hours). whenever the IDT82V3012 works in the holdover mode, the holdover pin will be set to logic high. 2.1.4 freerun mode the freerun mode is typically used when a master clock source is required, or used when a system is just powered up and the network synchronization has not been achieved. in this mode, the IDT82V3012 pr ovides timing and synchronization signals which are based on the master clock frequency (osci) only, and are not synchronized to the input reference signal. the accuracy of the output clock is equal to the accuracy of the master clock (osci). so if a 32 ppm output clock is required, the master clock must also be 32 ppm. refer to ?2.8 osc? for more information. whenever the IDT82V3012 works in the freerun mode, the freerun pin will be set to logic high. 2.2 frequency select circuit the input reference can be 8 khz, 1.544 mhz, 2.048 mhz or 19.44 mhz. the f0_sel1 and f0_sel0 pins select one of the four frequencies for the reference input 0 (fref0). the f1_sel1 and f1_sel0 pins select one of the four frequencies for the reference input 1 (fref1). see table - 2 and table - 3 for details. the reference inputs fref0 and fref1 may have different frequencies applied to them. every time the frequency is changed, the device must be reset to make the change effective. 2.3 reference input switch the IDT82V3012 accepts two simu ltaneous reference signals fref0 and fref1, and operates on the falling edge (8 khz, 1.544 mhz and 2.048 mhz) or rising edge (19.44 mh z). one of the two reference signals will be input to the device, as determined by the in_sel pin. see table - 2 fref0 frequency selection frequency selection pins fref0 input frequency f0_sel1 f0_sel0 0 0 19.44 mhz 01 8 khz 1 0 1.544 mhz 1 1 2.048 mhz table - 3 fref1 frequency selection frequency selection pins fref1 input frequency f1_sel1 f1_sel0 0 0 19.44 mhz 01 8 khz 1 0 1.544 mhz 1 1 2.048 mhz
11 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range table - 4 . the selected reference signal is sent to the tie control block, reference input monitor and invalid input signal detection block for further processing. when a transient voltage occurs on the in_sel pin, the operating mode will be changed to short time ho ldover (s4) with the tie control block automatically disabled. at t he stage of s4, if no in_sel transient occurs, the reference signal will be switched from one to the other, and the operating mode will be changed back to normal (s1) automatically. during the change from s4 to s1, the tie control block can be enabled or disabled, depending on the logic level on the tie_en pin. see figure - 3 for details. 2.4 reference input monitor the telcordia gr-1244-core standard recommends that the dpll should be able to reject the references that are off the nominal frequency by more than 12 ppm. t he IDT82V3012 monitors the fref0 and fref1 frequencies and outputs two signals at mon_out0 pin and mon_out1 pin to indicate the monitoring results respectively. whenever the fref0 frequency is off the nomi nal frequency by more than 12 ppm, the mon_out0 pin will go high. the mon_out1 pin indicates the monitoring result of fref1 in the same way. the mon_out0 and mon_out1 signals are updated every 2 seconds. 2.5 invalid input signal detection this circuit is used to detect if t he selected input reference (fref0 or fref1) is out of the capture range. refer to ?3.6 capture range? for details. this includes a complete loss of the input reference and a large frequency shift in the input reference. if the input reference is invalid (out of the capture range), the IDT82V3012 will be automatically c hanged to the holdover mode (auto- holdover). when the input reference becomes valid, the device will be changed back to the normal mode and the output signals will be locked to the input reference. in the holdover mode, the output signals are based on the output reference signal 30 ms to 60 ms prior to entering the holdover mode. the amount of phase drift while in holdover can be negligible because the holdover mode is very accurate (e.g., 0.025 ppm). consequently, the phase delay between the input and out put after switching back to the normal mode is preserved. 2.6 tie control block if the current reference is badly dam aged or lost, it is necessary to use the other reference or t he one generated by storage techniques instead. but when switching the reference, a step change in phase on the input reference will occur. a step change in phase in the input to dpll may lead to an unacceptable phase change on the output signals. the tie control block, when enabled, prevents a step change in phase on the input reference signals from causing a step change in phase on the output of the dpll block. figure - 4 shows the tie control block diagram. figure - 4 tie co ntrol block diagram when the tie control block is enabl ed manually or automatically (by the tie_en pin or tie auto-enable logic generated by the state control circuit), it works under the control of the step generation circuit. at the measure circuit stage, the selected reference signal (fref0 or fref1) is compared with the f eedback signal (current output feed back from the frequency select circuit) . the phase difference between the input reference and the feedback signal is stored in the storage circuit for tie correction. according to t he value stored in the storage circuit, the trigger circuit generates a virtual reference with the same phase as the previous reference. in this way, the reference can be switched without generating a step change in phase. figure - 5 shows the phase transient that will result if a reference switch is performed with t he tie control block enabled. the value of the phase differenc e in the storage circuit can be cleared by applying a logic low reset signal to the tclr pin. the minimum width of the reset pulse should be 300 ns. when the IDT82V3012 primarily ente rs the holdover mode for a short time period and then returns back to the normal mode, the tie control circuit should not be enabl ed. this will prevent undesired accumulated phase change between the input and output. if the tie control block is dis abled manually or automatically, a reference switch will result in a phase alignment between the input signal and the output signal as shown in figure - 6 . the slope of the phase adjustment is limited to 5 ns per 125 s. table - 4 input reference selection in_sel input reference 0fref0 1fref1 step generation tie_en reference select circuit fref0 fref1 in_sel measure circuit storage circuit trigger circuit feedback signal tclr fref virtual reference signal
12 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range figure - 5 reference switch with tie control block enabled figure - 6 reference switch with tie control block disabled 2.7 dpll block as shown in figure - 7 , the dpll block consists of a phase detector, a limiter, a loop filter, a digita l control oscillator and divider. 2.7.1 phase detector (phd) in the normal mode, the phase detector compares the virtual reference signal from the tie cont rol circuit with the feedback signal from the frequency select circuit, and outputs an error signal corresponding to the phase difference. this error signal is sent to the limiter circuit for phase slope control. in the freerun or holdover mode, the frequency select circuit, the phase detector and the limiter are inactive, and the input reference signal is not used. 2.7.2 limiter the limiter is used to limit t he phase slope. it ensures that the maximum output phase slope is limited to 5 ns per 125 s for all input transient conditions. this well m eets the at&t tr62411 and telcordia gr-1244-core specifications, whic h specify the maximum phase slope of 7.6 ns per 125 s and 81 ns per 1.326 ms respectively. input clock ref1 ref2 time = 0.00 s time = 0.25 s time = 0.50 s time = 0.75 s time = 1.0 s time = 1.25 s time = 1.50 s time = 1.75 s output clock input clock ref1 ref2 time = 0.00 s time = 0.25 s time = 0.50 s time = 0.75 s time = 1.0 s time = 1.25 s time = 1.50 s time = 1.75 s output clock
13 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range figure - 7 dpll block diagram in the normal mode, the limiter re ceives the error signal from the phase detector, limits the phase sl ope within 5 ns per 125 s and sends the limited signal to the loop filter. in the fast lock mode, the limiter is disabled, and the dpll locks to the input reference within 500 ms, whic h is much shorter than that in the normal mode. 2.7.3 loop filter the loop filter ensures that the jitter transfer meets the ets 300 011 and at&t tr62411 requirements. it works similarly to a first order low pass filter with 2.1 hz cutoff frequency for the four valid input frequencies (8 khz, 1.544 mhz, 2.048 mhz or 19.44 mhz). the output of the loop filter goes to the digital control oscillator directly or through the fraction bl ocks, in which e1, t1, c6 and c19 signals are generated. 2.7.4 fraction block by applying some algorithms to the incoming e1 signal, the fraction_c19, fraction_c6 and fr action_t1 blocks generate c19, c6 and t1 signals respectively. 2.7.5 digital control oscillator (dco) in the normal mode, the dco rece ives four limited and filtered signals from loop filter or fraction blocks. based on the values of the received signals, the dco generates four digital outputs: 19.44 mhz, 25.248 mhz, 32.768 mhz and 24.704 mhz for c19, c6, e1 and t1 dividers respectively. in the holdover mode, the dco is running at the same frequency as that generated by storage techniques. in the freerun mode, the dco is running at the same frequency as that of the master clock. 2.7.6 lock indicator if the output frequency of the dpll is identical to the input frequency, and the input phase offset is small enough so that no slope limiting is exhibited, the lock pin will be set high. 2.7.7 output interface the output interface uses three output signals from the dco to generate totally 9 types of clock si gnals and 7 types of framing signals all these output signals are synchronous to f8o. digital control oscillator c32o c16o c8o c4o c2o c3o c6o f0o f8o rsp tsp f16o c1.5o f32o output interface t1_divider e1_divider c6_divider frequency selection circuit 1 phase detector virtual reference fraction_c6 fraction_t1 24.704 mhz 32.768 mhz 25.248 mhz feedback signal limiter flock f1_sel1 f1_sel0 c19_divider 155.52 mhz f19o c19o apll 19.44 mhz fraction_c19 c19neg c19pos in_sel f0_sel1 f0_sel0 frequency selection circuit 0 c2/c1.5 loop filter fx_sel1 fx_sel0 (x = 0 or 1)
14 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range the 32.768 mhz signal is used by the e1_divider to generate five types of clock signals (c2o, c4o , c8o, c16o and c32o ) with nominal 50% duty cycle and six types of framing signals (f0o, f8o, f16o , f32o , rsp and tsp). the 24.704 mhz signal is used by the t1_divider to generate two types of t1 signals (c1.5o and c3o ) with nominal 50% duty cycle. the 25.248 mhz signal is used by the c6_divider to generate a c6o signal with nominal 50% duty cycle. the 19.44 mhz signal is sent to an apll, which outputs a 155.52 mhz signal. the 155.52 mhz signal is used by the c19_divider to generate 19.44 mhz clock signals (c 19o, c19pos and c19neg) with nominal 50% duty cycle and a framing signal f19o. additionally, the IDT82V3012 provides an output clock (c2/c1.5) with the frequency controlled by t he frequency selection pins fx_sel0 and fx_sel1 (see table - 5 for details). if the selected reference input (fref0 or fref1) is 8 khz, 2.048 mh z or 19.44 mhz, the c2/c1.5 pin will output a 2.048 mhz clock signal. if the selected reference input (fref0 or fref1) is 1.544 mhz, the c2/c1.5 pin will output a 1.544 mhz clock signal. the electrical and timing char acteristics of this output (2.048 mhz or 1.544 mhz) is the same as that of c2o or c1.5o. 2.8 osc the IDT82V3012 can use a clock as t he master timing source. in the freerun mode, the frequency tolerance of the clock outputs is identical to that of the source at the osci pin. for applications not requiring an accurate freerun mode, the tolerance of the master timing source may be 100 ppm. for applications requi ring an accurate freerun mode, such as at&t tr62411, the toleranc e of the master timing source must be no greater than 32 ppm. the desired capture range should be taken into consideration when determining the accuracy of the mast er timing source. the sum of the accuracy of the master timing source and the capture range of the IDT82V3012 will always equal 230 ppm . for example, if the master timing source is 100 ppm, the capture range will be 130 ppm. 2.8.1 clock oscillator when selecting a clock oscillato r, numerous parameters must be considered. this includes abs olute frequency, frequency change over temperature, output rise and fall ti mes, output levels and duty cycle. for applications requiring 32 ppm clock accuracy, the following clock oscillator module may be used. fox f7c-2e3-20.0 mhz frequency: 20.0 mhz tolerance: 25 ppm 0 c to 70 c rise & fall time: 10 ns (0.33 v, 2.97 v, 15 pf) duty cycle: 40% to 60% for stratum 3 application, the cl ock oscillator should meet the following requirements: frequency: 20.0 mhz tolerance: 4.6 ppm over 20 years life time drift: 0.04 ppm per day @ constant temperature 0.3 ppm over temperature range of 0 to 70 c the output clock should be connect ed directly (not ac coupled) to the osci input of the IDT82V3012, as shown in figure - 8 . figure - 8 clock oscillator circuit 2.9 jtag the IDT82V3012 supports ieee 1149.1 jtag scan. 2.10 reset, lock and tie application a simple power-up reset circuit is shown as figure - 9 . the logic low reset pulse is about 50 s. the resistor rp is used for protec tion only and limits current into the rst pin during power down. the logi c low reset pulse width is not critical but should be greater than 300 ns. when the dpll operates in normal mode after power-up or reset, the lock pin may indicate freque ncy lock before the output phase is synchronized with the input. the phase lock requires 30 seconds (at most) after frequency lock. if users want to switch the input reference, it is highly recommended to do the switch after phase lock, with tie control block enabled. after tie control block is cleared, the dpll requires some time for the phase relationship to stabilize. in general, the phase lock requires 30 seconds (at most) after frequency lock. table - 5 c2/c1.5 output frequency control frequency selection pins frefx input frequency c2/c1.5 output frequency fx_sel1 fx_sel0 0 0 19.44 mhz 2.048 mhz 0 1 8 khz 2.048 mhz 1 0 1.544 mhz 1.544 mhz 1 1 2.048 mhz 2.048 mhz note: ?x? can be 0 or 1, as selected by in_sel pin. in_sel = 0: x = 0, fref0 is the selected reference input. the frequency of fref0 is determined by f0_sel0 and f0_sel1 pins. in_sel = 1: x = 1, fref1 is the selected reference input. the frequency of fref1 is determined by f1_sel0 and f1_sel1 pins. +3.3 v 20 mhz out gnd +3.3 v osci IDT82V3012 0.1 f
15 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range figure - 9 power-up reset circuit 3.3 v r 10 k ? rp 1 k ? c 1 f rst IDT82V3012
16 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range 3 measures of perfor- mance the following are some synchronizer performance indicators and their corresponding definitions. 3.1 intrinsic jitter intrinsic jitter is the jitter produc ed by the synchronizing circuit and is measured at its output. it is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. intrinsic jitter may also be measured when the device is in a non- synchronizing mode, such as free r unning or holdover, by measuring the output jitter of the device. intrinsic ji tter is usually measured with various band limiting filters depending on the applicable standards. for the IDT82V3012, the intrinsic jitter is limited to less than 0.02 ui on the 2.048 mhz and 1.544 mhz clocks. 3.2 jitter tolerance jitter tolerance is a measure of the ability of a dpll to operate properly (i.e., remain in lock and or regain lock in the presence of large jitter magnitudes at various jitter fr equencies) when jitter is applied to its reference. the applied jitter m agnitude and jitter frequency depends on the applicable standards. 3.3 jitter transfer jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. input jitter is applied at various amplitudes and frequencies, and output jitter is measured with vari ous filters depending on the applicable standards. for the IDT82V3012, two internal elements determine the jitter attenuation. this includes the internal 2.1 hz low pass loop filter and the phase slope limiter. the phase slope lim iter limits the output phase slope to 5 ns per 125 s. therefore, if the input signal exceeds this rate, such as for very large amplitude, low frequency input jitter, the maximum output phase slope will be limited (i.e ., attenuated) to 5 ns per 125 s. the IDT82V3012 has 16 outputs with 4 possible input frequencies for a total of 64 possible jitter transfer functions. since all outputs are derived from the same signal, the jitter transfer values for the four cases, 8 khz to 8 khz, 1.544 mhz to 1.544 mhz, 2.048 mhz to 2.048 mhz and 19.44 mhz to 19.44 mhz can be applied to all outputs. it should be noted that 1 ui at 1.544 mhz is 644 ns, which is not equal to 1 ui at 2.048 mhz, which is 488 ns. consequently, a transfer value using different input and out put frequencies must be calculated in common units (e.g., seconds). using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs based on the four jitter transfer functions provided. note that the resu lting jitter transfer functions for all combinations of inputs (8 khz, 1.544 mhz, 2.048 mhz, 19.44 mhz) and outputs (8 khz, 1.544 mhz, 3.088 mhz, 6.312 mhz, 2.048 mhz, 4.096 mhz, 8.192 mhz, 16.384 mhz, 19.44 mhz, 32.768 mhz) for a given input signal (jitter frequency and jitter amplitude) are the same. since intrinsic jitter is always pr esent, jitter attenuation will appear to be lower for small input jitter signals than for large ones. consequently, accurate jitter transfer function measurements are usually made with large input jitter signals (e.g., 75% of the specified maximum jitter tolerance). 3.4 frequency accuracy frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an external reference, but is operating in a free running mode. for the IDT82V3012, the freerun accuracy is equal to the master clock (osci) accuracy. 3.5 holdover accuracy holdover accuracy is defined as the absolute tolerance of an output clock signal, when it is not locked to an external reference signal, but is operating using storage techniques . for the IDT82V3012, the storage value is determined while the device is in normal mode and locked to an external reference signal. the absolute master clock (osci) accuracy of the IDT82V3012 does not affect holdover accuracy, but the change in osci accuracy while in holdover mode does. 3.6 capture range also referred to as pull-in rang e. this is the input frequency range over which the synchronizer must be able to pull into synchronization. the IDT82V3012 capture range is equal to 230 ppm minus the accuracy of the master clock (osci). for example, a 32 ppm master clock results in a capture range of 198 ppm. the telcordia gr-1244-core standard, recommends that the dpll should be able to reject references that are off the nominal frequency by more than 12 ppm. the IDT82V3012 provides two pins, mon_out0 and mon_out1, to respectively indicate whether the reference inputs fref0 and fref1 are within 12 ppm of the nominal frequency. 3.7 lock range this is the input frequency range over which the synchronizer must be able to maintain synchronization. the lock range is equal to the capture range for the IDT82V3012. 3.8 phase slope phase slope is measured in seconds per second and is the rate at which a given signal changes phase wi th respect to an ideal signal. the given signal is typically the output si gnal. the ideal signal is of constant frequency and is nominally equal to the value of the final output signal or final input signal. 3.9 time interval error (tie) tie is the time delay between a given timing signal and an ideal timing signal. 3.10 maximum time interval error (mtie) mtie is the maximum peak to peak delay between a given timing signal and an ideal timing signal with in a particular observation period.
17 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range 3.11 phase continuity phase continuity is the phase difference between a given timing signal and an ideal timing signal at the end of a particular observation period. usually, the given timing si gnal and the ideal timing signal are of the same frequency. phase continuity applies to the output of the synchronizer after a signal disturbance due to a mode change. the observation period is usually the time from the disturbance, to just after the synchronizer has settled to a steady state. in the case of the IDT82V3012, the output signal phase continuity is maintained to within 5 ns at the instance (over one frame) of all mode changes. the total phase shift, depending on the type of mode change, may accumulate up to 200 ns over many frames. the rate of change of the 200 ns phase shift is limited to a maximum phase slope of approximately 5 ns per 125 s. this meets the at&t tr62411 maximum phase slope requirement of 7.6 ns per 125 s and telcordia gr-1244-core (81 ns per 1.326 ms). 3.12 phase lock time this is the time it takes the synchronizer to phase lock to the input signal. phase lock occurs when th e input signal and output signal are not changing in phase with respect to each other (not including jitter). lock time is very difficult to determine because it is affected by many factors including: 1. initial input to output phase difference 2. initial input to output frequency difference 3. synchronizer loop filter 4. synchronizer limiter although a short lock time is desirabl e, it is not always possible to achieve due to other synchronizer r equirements. for instance, better jitter transfer performance is achi eved with a lower frequency loop filter which increases lock time. and better (smaller) phase slope performance (limiter) results in longer lock times. the IDT82V3012 loop filter and limiter are optimized to m eet the at&t tr62411 jitter transfer and phase slope requirements. cons equently, phase lock time, which is not a standard requirement, may be lo nger than in other applications. see ?7.1 performance? for details. the IDT82V3012 provides a floc k pin to enable the fast lock mode. when this pin is set to hi gh, the dpll will lock to an input reference within approximately 500 ms.
18 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range 4 absolute maximum ratings note: stresses greater than those listed under absolu te maximum ratings may cause permanent da mage to the device. this is a stress r ating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 5 recommended dc op erating conditions 6 dc electrical characteristics 6.1 single end input/output port * note: 1. voltages are with respect to ground (v ss ) unless otherwise stated. 2. supply voltage and operating te mperature are as per recommende d operating conditions. ratings min. max. unit power supply voltage -0.5 5.0 v voltage on any pin with respect to ground -0.5 5.5 v package power dissipation 200 mw storage temperature -55 125 c parameter min. max. unit operating temperature -40 +85 c power supply voltage 3.0 3.6 v parameter description min. typ. max. units test conditions * i dds supply current with osci = 0 v 10 ma outputs unloaded i dd supply current with osci = clock 60 ma outputs unloaded v cih cmos high-level input voltage 0.7v dd v osci, fref0 and fref1 v cil cmos low-level input voltage 0.3v dd v osci, fref0 and fref1 v tih ttl high-level input voltage 2.0 v all input pins except for osci, fref0 and fref1 v til ttl low-level input voltage 0.8 v all input pins except for osci, fref0 and fref1 i il input leakage current: a v i = v dd or 0 v normal (low level) -15 15 normal (high level) -15 15 pull up (low level) -100 0 pull up (high level) -15 15 pull down (low level) -15 15 pull down (high level) 0 100 v oh high-level output voltage 2.4 v i oh = 8 ma v ol low-level output voltage 0.4 v i ol = 8 ma
19 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range 6.2 differential output port (lvds) parameter description min. typ. max. units test conditions vod differential output voltage 250 350 450 mv rl = 100 ? ? vod change in magnitude of vod for complementary output states 4 35 mv rl = 100 ? vos offset voltage 1.125 1.25 1.375 v rl = 100 ? ? vos change in magnitude of vos for complementary output states 5 25 mv rl = 100 ? voh output voltage high 1.38 1.6 v rl = 100 ? vol output voltage low 0.9 1.03 v rl = 100 ? t tlh output rise time 0.38 1.5 ns rl = 100 ? t thl output fall time 0.40 1.5 ns rl = 100 ? ios output short circuit current 6.0 ma iosd differential output short circuit current 6.0 10 ma
20 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range 7 ac electrical characteristics 7.1 performance description min. typ. max. units test conditions / notes (see ?notes? on page 25) freerun mode accuracy with osci at: 0 ppm -0 +0 ppm 5-9 freerun mode accuracy with osci at: 32 ppm -32 +32 ppm 5-9 freerun mode accuracy with osci at: 100 ppm -100 +100 ppm 5-9 holdover mode accuracy with osci at: 0 ppm -0.025 +0.025 ppm 1, 2, 4, 6-9, 43, 44 holdover mode accuracy with osci at: 32 ppm -0.025 +0.025 ppm 1, 2, 4, 6-9, 43, 44 holdover mode accuracy with osci at: 100 ppm -0.025 +0.025 ppm 1, 2, 4, 6-9, 43, 44 capture range with osci at: 0 ppm -230 +230 ppm 1-3, 6-9 capture range with osci at: 32 ppm -198 +198 ppm 1-3, 6-9 capture range with osci at: 100 ppm -130 +130 ppm 1-3, 6-9 phase lock time 50 s 1-3, 6-15, 45 output phase continuity with reference switch 200 ns 1-3, 6-15 output phase continuity with mode switch to normal 200 ns 1-2, 4-15 output phase continuity with mode switch to freerun 200 ns 1-4, 6-15 output phase continuity with mode switch to holdover 50 ns 1-3, 6-15 fref0 frequency accuracy when mon_out0 is logic low -12 +12 ppm fref1 frequency accuracy when mon_out1 is logic low -12 +12 ppm mtie (maximum time interval error) 600 ns 1-15, 28 output phase slope 40 s/s 1-15, 28 reference input for auto-holdover with 8 khz -18 k +18 k ppm 1-3, 6, 10-12 reference input for auto-holdover with 1.544 mhz -36 k +36 k ppm 1-3, 7, 10-12 reference input for auto-holdover with 2.048 mhz -36 k +36 k ppm 1-3, 8, 10-12 reference input for auto-h oldover with 19.44 mhz -36 k +36 k ppm 1-3, 9, 10-12
21 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range 7.2 intrinsic jitter unfiltered 7.3 c1.5o (1.544 mhz) intrinsic jitter filtered 7.4 c2o (2.048 mhz) in trinsic jitter filtered 7.5 c19o (19.44 mhz) in trinsic jitter filtered description min. typ. max. units test conditions / notes (see ?notes? on page 25) intrinsic jitter at f8o (8 khz) 0.0001 uipp 1-15, 22-25, 29 intrinsic jitter at f0o (8 khz) 0.0001 uipp 1-15, 22-25, 29 intrinsic jitter at f16o (8 khz) 0.0001 uipp 1-15, 22-25, 29 intrinsic jitter at c1.5o (1.544 mhz) 0.015 uipp 1-15, 22-25, 30 intrinsic jitter at c3o (3.088 mhz) 0.03 uipp 1-15, 22-25, 32 intrinsic jitter at c2o (2.048 mhz) 0.01 uipp 1-15, 22-25, 31 intrinsic jitter at c6o (6.312 mhz) 0.06 uipp 1-15, 22-25, 34 intrinsic jitter at c4o (4.096 mhz) 0.02 uipp 1-15, 22-25, 33 intrinsic jitter at c8o (8.192 mhz) 0.04 uipp 1-15, 22-25, 35 intrinsic jitter at c16o (16.834 mhz) 0.04 uipp 1-15, 22-25, 36 intrinsic jitter at tsp (8 khz) 0.0001 uipp 1-15, 22-25, 29 intrinsic jitter at rsp (8 khz) 0.0001 uipp 1-15, 22-25, 29 intrinsic jitter at c32o (32.768 mhz) 0.08 uipp 1-15, 22-25, 38 description min. typ. max. units test conditions / notes (see ?notes? on page 25) intrinsic jitter (4 hz to 100 khz filter) 0.008 uipp 1-15, 22-25, 30 intrinsic jitter (10 hz to 40 khz filter) 0.006 uipp 1-15, 22-25, 30 intrinsic jitter (8 khz to 40 khz filter) 0.006 uipp 1-15, 22-25, 30 intrinsic jitter (10 hz to 8 khz filter) 0.003 uipp 1-15, 22-25, 30 description min. typ. max. units test conditions / notes (see ?notes? on page 25) intrinsic jitter (4 hz to 100 khz filter) 0.005 uipp 1-15, 22-25, 31 intrinsic jitter (10 hz to 40 khz filter) 0.004 uipp 1-15, 22-25, 31 intrinsic jitter (8 khz to 40 khz filter) 0.003 uipp 1-15, 22-25, 31 intrinsic jitter (10 hz to 8 khz filter) 0.002 uipp 1-15, 22-25, 31 description min. typ. max. units test conditions / notes (see ?notes? on page 25) intrinsic jitter (500 hz to 1.3 mhz filter) 0.4 0.5 nspp 1-15, 22-25, 37 intrinsic jitter (65 khz to 1.3 mhz filter) 0.2 0.3 nspp 1-15, 22-25, 37
22 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range 7.6 8 khz input to 8 kh z output jitter transfer 7.7 1.544 mhz input to 1.544 mhz output jitter transfer 7.8 2.048 mhz input to 2.048 mhz output jitter transfer description min. typ. max. units test conditions / notes (see ?notes? on page 25) jitter attenuation for 1 hz@0.01 uipp input 0 6 db 1-3, 6, 10-15, 22-23, 25, 29, 39 jitter attenuation for 1 hz@0.54 uipp input 6 16 db 1-3, 6, 10-15, 22-23, 25, 29, 39 jitter attenuation for 10 hz@0.10 uipp input 15 22 db 1-3, 6, 10-15, 22-23, 25, 29, 39 jitter attenuation for 60 hz@0.10 uipp input 32 38 db 1-3, 6, 10-15, 22-23, 25, 29, 39 jitter attenuation for 300 hz@0.10 uipp input 42 db 1-3, 6, 10-15, 22-23, 25, 29, 39 jitter attenuation for 3600 hz@0.005 uipp input 50 db 1-3, 6, 10-15, 22-23, 25, 29, 39 description min. typ. max. units test conditions / notes (see ?notes? on page 25) jitter attenuation for 1 hz@20 uipp input 0 6 db 1-3, 7, 10-15, 22-23, 25, 30, 39 jitter attenuation for 1 hz@104 uipp input 6 16 db 1-3, 7, 10-15, 22-23, 25, 30, 39 jitter attenuation for 10 hz@20 uipp input 17 22 db 1-3, 7, 10-15, 22-23, 25, 30, 39 jitter attenuation for 60 hz@20 uipp input 33 38 db 1-3, 7, 10-15, 22-23, 25, 30, 39 jitter attenuation for 300 hz@20 uipp input 45 db 1-3, 7, 10-15, 22-23, 25, 30, 39 jitter attenuation for 10 khz@0.3 uipp input 48 db 1-3, 7, 10-15, 22-23, 25, 30, 39 jitter attenuation for 40 khz@0.3 uipp input 50 db 1-3, 7, 10-15, 22-23, 25, 30, 39 description min. typ. max. units test conditions / notes (see ?notes? on page 25) jitter at output for 1 hz@3.00 uipp input 2.5 uipp 1-3, 8, 10-15, 22-23, 25, 31, 39 jitter at output for 1 hz@3.00 uipp input with 40 hz to 100 khz filter 0.07 uipp 1-3, 8, 10-15, 22-23, 25, 31, 40 jitter at output for 3 hz@2.33 uipp input 1.4 uipp 1-3, 8, 10-15, 22-23, 25, 31, 39 jitter at output for 3 hz@2.33 uipp input with 40 hz to 100 khz filter 0.10 uipp 1-3, 8, 10-15, 22-23, 25, 31, 40 jitter at output for 5 hz@2.07 uipp input 0.90 uipp 1-3, 8, 10-15, 22-23, 25, 31, 39 jitter at output for 5 hz@2.07 uipp input with 40 hz to 100 khz filter 0.10 uipp 1-3, 8, 10-15, 22-23, 25, 31, 40 jitter at output for 10 hz@1.76 uipp input 0.40 uipp 1-3, 8, 10-15, 22-23, 25, 31, 39 jitter at output for 10 hz@1.76 uipp i nput with 40 hz to 100 khz filter 0.10 uipp 1-3, 8, 10-15, 22-23, 25, 31, 40 jitter at output for 100 hz@1.50 uipp input 0.06 uipp 1-3, 8, 10-15, 22-23, 25, 31, 39 jitter at output for 100 hz@1.50 uipp input with 40 hz to 100 khz filter 0.05 uipp 1-3, 8, 10-15, 22-23, 25, 31, 40 jitter at output for 2400 hz@1.50 uipp input 0.04 uipp 1-3, 8, 10-15, 22-23, 25, 31, 39 jitter at output for 2400 hz@1.50 uipp input with 40 hz to 100 khz filter 0.03 uipp 1-3, 8, 10-15, 22-23, 25, 31, 40 jitter at output for 100 khz@0.20 uipp input 0.04 uipp 1-3, 8, 10-15, 22-23, 25, 31, 39 jitter at output for 100 khz@0.20 uipp input with 40 hz to 100 khz filter 0.02 uipp 1-3, 8, 10-15, 22-23, 25, 31, 40
23 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range 7.9 19.44 mhz input to 19.44 mh z output jitter transfer 7.10 8 khz input jitter tolerance 7.11 1.544 mhz input jitter tolerance description min. typ. max. units test conditions / notes (see ?notes? on page 25) jitter attenuation for 1 hz@20 uipp input 0 6 db 1-3, 9-15, 22-23, 25, 37, 39 jitter attenuation for 1 hz@104 uipp input 6 16 db 1-3, 9-15, 22-23, 25, 37, 39 jitter attenuation for 10 hz@20 uipp input 17 22 db 1-3, 9-15, 22-23, 25, 37, 39 jitter attenuation for 60 hz@20 uipp input 33 38 db 1-3, 9-15, 22-23, 25, 37, 39 jitter attenuation for 300 hz@20 uipp input 45 db 1-3, 9-15, 22-23, 25, 37, 39 jitter attenuation for 10 khz@0.3 uipp input 48 db 1-3, 9-15, 22-23, 25, 37, 39 jitter attenuation for 40 khz@0.3 uipp input 50 db 1-3, 9-15, 22-23, 25, 37, 39 description min. typ. max. units test conditions / notes (see ?notes? on page 25) jitter tolerance for 1 hz input 0.80 uipp 1-3, 6, 10-15, 22-23, 25-27, 29 jitter tolerance for 5 hz input 0.70 uipp 1-3, 6, 10-15, 22-23, 25-27, 29 jitter tolerance for 20 hz input 0.60 uipp 1-3, 6, 10-15, 22-23, 25-27, 29 jitter tolerance for 300 hz input 0.16 uipp 1-3, 6, 10-15, 22-23, 25-27, 29 jitter tolerance for 400 hz input 0.14 uipp 1-3, 6, 10-15, 22-23, 25-27, 29 jitter tolerance for 700 hz input 0.07 uipp 1-3, 6, 10-15, 22-23, 25-27, 29 jitter tolerance for 2400 hz input 0.02 uipp 1-3, 6, 10-15, 22-23, 25-27, 29 jitter tolerance for 3600 hz input 0.01 uipp 1-3, 6, 10-15, 22-23, 25-27, 29 description min. typ. max. units test conditions / notes (see ?notes? on page 25) jitter tolerance for 1 hz input 150 uipp 1-3, 7, 10-15, 22-23, 25-27, 30 jitter tolerance for 5 hz input 140 uipp 1-3, 7, 10-15, 22-23, 25-27, 30 jitter tolerance for 20 hz input 130 uipp 1-3, 7, 10-15, 22-23, 25-27, 30 jitter tolerance for 300 hz input 38 uipp 1-3, 7, 10-15, 22-23, 25-27, 30 jitter tolerance for 400 hz input 25 uipp 1-3, 7, 10-15, 22-23, 25-27, 30 jitter tolerance for 700 hz input 15 uipp 1-3, 7, 10-15, 22-23, 25-27, 30 jitter tolerance for 2400 hz input 5 uipp 1-3, 7, 10-15, 22-23, 25-27, 30 jitter tolerance for 10 khz input 1.2 uipp 1-3, 7, 10-15, 22-23, 25-27, 30 jitter tolerance for 40 khz input 0.5 uipp 1-3, 7, 10-15, 22-23, 25-27, 30
24 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range 7.12 2.048 mhz input jitter tolerance 7.13 19.44 mhz input jitter tolerance description min. typ. max. units test conditions / notes (see ?notes? on page 25) jitter tolerance for 1 hz input 150 uipp 1-3, 8, 10-15, 22-23, 25-27, 31 jitter tolerance for 5 hz input 140 uipp 1-3, 8, 10-15, 22-23, 25-27, 31 jitter tolerance for 20 hz input 130 uipp 1-3, 8, 10-15, 22-23, 25-27, 31 jitter tolerance for 300 hz input 40 uipp 1-3, 8, 10-15, 22-23, 25-27, 31 jitter tolerance for 400 hz input 33 uipp 1-3, 8, 10-15, 22-23, 25-27, 31 jitter tolerance for 700 hz input 18 uipp 1-3, 8, 10-15, 22-23, 25-27, 31 jitter tolerance for 2400 hz input 5.5 uipp 1-3, 8, 10-15, 22-23, 25-27, 31 jitter tolerance for 10 khz input 1.3 uipp 1-3, 8, 10-15, 22-23, 25-27, 31 jitter tolerance for 100 khz input 0.4 uipp 1-3, 8, 10-15, 22-23, 25-27, 31 description min. typ. max. units test conditions / notes (see ?notes? on page 25) jitter tolerance for 12 hz input 2800 uipp 1-3, 9-15, 22-23, 25-27, 37 jitter tolerance for 178 hz input 2800 uipp 1-3, 9-15, 22-23, 25-27, 37 jitter tolerance for 0.0016 hz input 311 uipp 1-3, 9-15, 22-23, 25-27, 37 jitter tolerance for 0.0156 hz input 311 uipp 1-3, 9-15, 22-23, 25-27, 37 jitter tolerance for 0.125 hz input 39 uipp 1-3, 9-15, 22-23, 25-27, 37 jitter tolerance for 19.3 hz input 39 uipp 1-3, 9-15, 22-23, 25-27, 37 jitter tolerance for 500 hz input 1.5 uipp 1-3, 9-15, 22-23, 25-27, 37 jitter tolerance for 6.5 khz input 1.5 uipp 1-3, 9-15, 22-23, 25-27, 37 jitter tolerance for 65 khz input 0.15 uipp 1-3, 9-15, 22-23, 25-27, 37 jitter tolerance for 1.3 mhz input 0.15 uipp 1-3, 9-15, 22-23, 25-27, 37
25 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range notes: voltages are with respect to ground (v ss ) unless otherwise stated. supply voltage and operating temperature are as per re commended operating conditions. timing parameters are as per timing parameter measurement voltage levels. 1. fref0 reference input selected. 2. fref1 reference input selected. 3. normal mode selected. 4. holdover mode selected. 5. freerun mode selected. 6. 8 khz frequency mode selected. 7. 1.544 mhz frequency mode selected. 8. 2.048 mhz frequency mode selected. 9. 19.44 mhz frequency mode selected. 10. master clock input osci at 20 mhz 0 ppm. 11. master clock input osci at 20 mhz 32 ppm. 12. master clock input osci at 20 mhz 100 ppm. 13. selected reference input at 0 ppm. 14. selected reference input at 32 ppm. 15. selected reference input at 100 ppm. 16. for freerun mode of 0 ppm. 17. for freerun mode of 32 ppm. 18. for freerun mode of 100 ppm. 19. for capture range of 230 ppm. 20. for capture range of 198 ppm. 21. for capture range of 130 ppm. 22. 25 pf capacitive load. 23. osci master clock jitter is less than 2 nspp, or 0.04 uipp where 1 uipp = 1/20 mhz. 24. jitter on reference input is less than 7 nspp. 25. applied jitter is sinusoidal. 26. minimum applied input jitter magni tude to regain synchronization. 27. loss of synchronization is obtained at slightly higher input jitter amplitudes. 28. within 10 ms of the state, reference or input change. 29. 1 uipp = 125 s for 8 khz signals. 30. 1 uipp = 648 ns for 1.544 mhz signals. 31. 1 uipp = 488 ns for 2.048 mhz signals. 32. 1 uipp = 323 ns for 3.088 mhz signals. 33. 1 uipp = 244 ns for 4.096 mhz signals. 34. 1 uipp = 158 ns for 6.312 mhz signals. 35. 1 uipp = 122 ns for 8.192 mhz signals. 36. 1 uipp = 61 ns for 16.484 mhz signals. 37. 1 uipp = 51 ns for 19.44 mhz signals. 38. 1 uipp = 30 ns for 32.968 mhz signals. 39. no filter. 40. 40 hz to 100 khz bandpass filter. 41. with respect to reference input signal frequency. 42. after a rst or tclr . 43. master clock duty 40% to 60%. 44. prior to holdover mode, device as in normal mode and phase locked. 45. with input frequency offset of 100 ppm.
26 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range 8 timing characteristics 8.1 timing parameter meas urement voltage levels figure - 10 timing parameter measurement voltage levels notes: 1. voltages are with respect to ground (v ss ) unless otherwise stated. 2. supply voltage and operating temperature are as per recommended operating conditions. 3. timing for input and output signals is based on the worst case result of the cmos thresholds. 8.2 input/output timing parameter description cmos units v t threshold voltage 0.5v dd v v hm rise and fall threshold voltage high 0.7v dd v v lm rise and fall threshold voltage low 0.3v dd v parameter description min. typ. max. units test conditions t rw reference input pulse width high or low 51 ns 8 khz, 1.544 mhz or 2.048 mhz reference input 5 ns 19.44 mhz reference input t irf reference input rise or fall time 10 ns t r8d 8 khz reference input to f8o delay 8 ns t r15d 1.544 mhz reference input to f8o delay 332 ns t r2d 2.048 mhz reference input to f8o delay 253 ns t r19d 19.44 mhz reference input to f8o delay 8 ns t f0d f8o to f0o delay 118 121 124 ns t f16s f16o setup to c16o falling 25 40 ns t f16h f16o hold to c16o falling 25 40 ns t f19s f19o setup to c19o falling 20 35 ns t f19h f19o hold to c19o falling 20 35 ns t c15d f8o to c1.5o delay -3 0 +3 ns t c3d f8o to c3o delay -3 1.6 +3 ns t c6d f8o to c6o delay -3 1.6 +3 ns t c2d f8o to c2o -2 0 +2 ns t c4d f8o to c4o -2 0 +2 ns t c8d f8o to c8o delay -2 0 +2 ns t c16d f8o to c16o delay -2 0 +2 ns timing reference points t irf, t orf t irf, t orf v hm v t v lm all siganls
27 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range t c19d f8o to c19o delay -8 0 +8 ns t c32d f8o to c32o delay -2 2 +2 ns t tspd f8o to tsp delay -3 0 +3 ns t rspd f8o to rsp delay -3 0 +3 ns t c15w c1.5o pulse width high or low 323 ns t c3w c3o pulse width high or low 161 ns t c6w c6o pulse width high or low 82 ns t c2w c2o pulse width high or low 244 ns t c4w c4o pulse width high or low 122 ns t c8w c8o pulse width high or low 61 ns t c16w c16o pulse width high or low 30.5 ns t c19w c19o pulse width high or low 25 ns t c32wh c32o pulse width high 14.4 ns t tspw tsp pulse width high 486 ns t rspw rsp pulse width high 490 ns t f0wl f0o pulse width low 243 ns t f8wh f8o pulse width high 123.6 ns t f16wl f16o pulse width low 60.9 ns t f19wh f19o pulse width high 25 ns t 0rf output clock and frame pulse rise or fall time 3 ns t s input controls setup time 100 ns t h input controls hold time 100 ns t f16d f8o to f16o delay 27.1 30.1 33.1 ns t f19d f8o to f19o delay 17 25 33 ns t f32d f8o to f32o delay 12 15.8 19 ns t f32s f32o setup to c32o falling 11 ns t f32h f32o hold to c32o falling 11 ns t f32wl f32o pulse width low 30.6 ns parameter description min. typ. max. units test conditions
28 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range figure - 11 input to ou tput timing (normal mode) t r8d t rw t r15d t rw fref0/fref1 8 khz fref0/fref1 1.544 mhz fref0/fref1 2.048 mhz f8o fref0/fref1 19.44 mhz t r2d t rw t rw t r19d v t v t v t v t v t
29 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range figure - 12 output timing 1 t f8wh t f0d t f0wl t f16d t f16wl t f16h t f16s t c16d t c16w t c8w t c4w t c2w t c2d t c6w t c6d t c15d t c15w t c8d t c4d v t v t v t v t v t v t v t v t v t c1.5o c6o c2o c4o c8o c16o f16o f0o f8o c32o c3o t c32d t c3d t c3w t c32wh v t v t f32o t f32wl t f32d v t t f32s t f32h t c6w t c4w t c8w v t c19o c19pos c19neg v t v t t c19d t c19w v t t f19wh t f19d t f19s t f19h f19o t c19w t c19d t c19d t c19w (see note 1) (see note 1)
30 IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range figure - 13 output timing 2 note 1: the timing characteristic of c2/c1.5 (2.048 mhz or 1.544 mhz) is the same as that of c2o or c1.5o. figure - 14 input cont rol setup and hold timing f8o c2o rsp tsp t rspd t rspw t tspd t tspw v t v t v t v t v t v t t h t s f8o mode_sel0 mode_sel1 tie_en in_sel
IDT82V3012 t1/e1/oc3 wan pll with dual reference inputs industrial temperature range 31 corporate headquarters 2975 stender way santa clara, ca 95054 for sales: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com for tech support: email: telecomhelp@idt.com phone: 408-330-1552 9 ordering information datasheet document history 07/21/2003 pgs. 7, 8, 17 10/22/2003 pgs. 1, 10, 11, 19, 20, 25, 26 02/02/2004 pgs. 14, 15 11/18/2004 pgs. 1, 10, 31 idt xxxxxxx xx x device type blank process/ temperature range 82v3012 industrial (-40 c to +85 c) t1/e1/oc3 wan pll with dual reference inputs package pv shrink small outline package (ssop, pv56) pvg green - shrink small outline package (ssop, pvg56)

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